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Features
* * * * * * * * * * * * * * * * * *
Two Different IF Receiving Bandwidth Versions Are Available (BIF = 300 kHz or 600 kHz) 5 V to 20 V Automotive Compatible Data Interface IC Condition Indicator, Sleep or Active Mode Low Power Consumption Due to Configurable Self Polling with a Programmable Timeframe Check High Sensitivity, Especially at Low Data Rates Data Clock Available for Manchester- and Bi-phase-coded Signals Minimal External Circuitry Requirements, no RF Components on the PC Board Except Matching to the Receiver Antenna Sensitivity Reduction Possible Even While Receiving Fully Integrated VCO SO20 Package Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40C to +105C Single-ended RF Input for Easy Adaptation to /4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level ESD Protection According to MIL-STD. 883 (4KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Frontend Filter. Up to 40 dB is Thereby Achievable With State-of-the-art SAWs. Communication to Microcontroller Possible Via a Single, Bi-directional Data Line Power Management (Polling) Is Also Possible by Means of a Separate Pin Via the Microcontroller Programmable Digital Noise Suppression
UHF ASK/FSK Receiver T5743 Preliminary
Description
The T5743 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the statements made below refer to 433.92 MHz and 315 MHz applications.
System Block Diagram
Figure 1. System Block Diagram
UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver
U2741B
T5743
Demod. Control 1...5 C
XTO
PLL
IF Amp
Antenna VCO
Antenna PLL XTO
Power amp.
LNA
VCO
Rev. 4569A-RKE-12/02
1
Pin Configuration
Figure 2. Pinning SO20
1 20
SENS
DATA
IC_ACTIVE
2
19
POLLING/_ON
CDEM
3
18
DGND
AVCC
4
17
DATA_CLK
TEST
5
16
MODE
T5743
AGND 6 15 DVCC
MIXVCC
7
14
XTO
LNAGND
8
13
LFGND
LNA_IN
9
12
LF
n.c. 10
11
LFVCC
Pin Description
Pin 1 2 Symbol SENS IC_ACTIVE Function Sensitivity-control resistor IC condition indicator Low = sleep mode High = active mode Lower cut-off frequency data filter Analog power supply Test pin, during operation at GND Analog ground Power supply mixer High-frequency ground LNA and mixer RF input Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator
3 4 5 6 7 8 9 10 11 12 13 14
CDEM AVCC TEST AGND MIXVCC LNAGND LNA_IN n.c. LFVCC LF LFGND XTO
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Pin Description (Continued)
Pin 15 16 Symbol DVCC MODE Function Digital power supply Selecting 433.92 MHz/315 MHz Low: fXT0 = 4.90625 MHz (USA) High: fXT0 = 6.76438 MHz (Europe) Bit clock of data stream Digital ground Selects polling or receiving mode Low: receiving mode High: polling mode Data output/configuration input
17 18 19
DATA_CLK DGND POLLING/_ON
20
DATA
Figure 3. Block Diagram
CDEM AVCC SENS
FSK/ASKDemodulator and data filter RSSI
Dem_out
Data interface
DATA
Limiter out POLLING/_ON IF Amp Sensitivity reduction Polling circuit and control logic TEST DATA_CLK MODE 4. Order FE CLK DVCC IC_ACTIVE LPF 3 MHz
AGND DGND
MIXVCC
Standby logic LFGND
LNAGND IF Amp
LFVCC
LPF 3 MHz
VCO
XTO
XTO
f LNA_IN LNA 64 LF
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RF Front-end
The RF front-end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal. According to Figure 3, the front-end consists of an LNA (low-noise amplifier), LO (local oscillator), a mixer and an RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64. The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to Figure 4, the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. Figure 4. PLL Peripherals
VS DVCC CL XTO
LFGND
LF VS R1 C9 C10
R1 = 820 W C9 = 4.7 nF C10 = 1 nF
LFVCC
The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 4 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason please notify that the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO cannot settle in time before the bit check starts to evaluate the incoming data stream. Self polling does therefore also not work in that case. fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: fLO = fRF - fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO. This relation is dependent on the logic level at Pin MODE.
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This is described by the following formulas: f LO MODE = 0 (USA) : f IF = --------314 f LO MODE = 1 (Europe) : f IF = ----------------432.92 The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where fRF = 315 MHz, MODE must be set to `0'. In the case of fRF = 433.92 MHz, MODE must be set to `1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at Pin MODE and on fRF. Table 1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver T5743 exhibits its highest sensitivity at the best signal-tonoise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network a mirror frequency suppression of DP Ref = 40 dB can be achieved. There are SAWs available that exhibit a notch at Df = 2 MHz. These SAWs work best for an intermediate frequency of fIF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 5 shows a typical input matching network, for f RF = 315 MHz and f R F = 433.92 MHz using a SAW. Figure 6 illustrates an according input matching to 50 W without a SAW. The input matching networks shown in Figure 6 are the reference networks for the parameters given in the electrical characteristics. Table 1. Calculation of LO and IF Frequency
Conditions Local Oscillator Frequency Intermediate Frequency
fRF = 315 MHz, MODE = 0 fRF = 433.92 MHz, MODE = 1 300 MHz < fRF < 365 MHz, MODE = 0
fLO = 314 MHz fLO = 432.92 MHz
f RF f LO = ------------------1 1 + --------314 f RF f LO = --------------------------1 1 + ----------------432.92
fIF = 1 MHz fIF = 1 MHz
f LO f IF = --------314
365 MHz < fRF < 450 MHz, MODE = 1
f LO f IF = ----------------432.92
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Figure 5. Input Matching Network with SAW Filter
8 LNAGND 8 LNAGND
T5743
C3 22p L 25n 9 LNA_IN C3 47p L 25n 9
T5743
LNA_IN
C16
C17 8.2p TOKO LL2012 F27NJ
C16
C17 22p TOKO LL2012 F47NJ
100p
fRF = 433.92 MHz
L2 TOKO LL2012 F33NJ C2 8.2p 33n
L3 27n
100p
fRF = 315 MHz
L3 47n
RFIN
1
IN
2
OUT OUT_GND IN_GND CASE_GND 3,4 7,8
B3555
5 6
RFIN C2 10p
L2 TOKO LL2012 F82NJ 82n
1
IN
2
OUT OUT_GND IN_GND CASE_GND 3,4 7,8
B3551
5 6
Figure 6. Input Matching Network without SAW Filter
fRF = 433.92 MHz
8 LNAGND
fRF = 315 MHz
8
LNAGND
T5743
9 15p 25n LNA_IN 9 33p 25n
T5743
LNA_IN
RFIN 3.3p 22n
RFIN 100p TOKO LL2012 F22NJ 3.3p 39n 100p TOKO LL2012 F39NJ
Please notify that for all coupling conditions (see Figure 5 and Figure 6), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB.
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Analog Signal Processing IF Amplifier
The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies refer to Table 1 to determine the center frequency. The T5743 is available with two different IF bandwidths. T5743P3, the version with BIF = 300 kHz, is well suited for ASK systems where Atmel's PLL transmitter U2741B is used. The receiver T5743P6 employs an IF bandwidth of BIF = 600 kHz. Both versions can be used together with the U2741B in ASK and FSK mode. If used in ASK applications, it allows higher tolerances for the receiver and PLL transmitter crystals. SAW transmitters exhibit much higher transmit freqeuncy tolerances compared to PLL transmitters. Generally, it is necessary to use BIF = 600 kHz together with such transmitters.
RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier. The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSens. RSens is connected between Pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means it is possible to operate the receiver at a lower sensitivity. If RSens is connected to GND, the receiver operates at full sensitivity. If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSens, the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 6 and exhibits the best possible sensitivity. R Sens can be connected to V S or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 7 is issued at Pin DATA to indicate that the receiver is still active (see also figure 34). Figure 7. Steady L State Limited DATA Output Pattern
DATA t DATA_min t DATA_L_max
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FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic `L' sets the demodulator to FSK, applying `H' to ASK mode. In ASK mode, an automatic threshold control circuit (ATC) is used to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit effectively suppresses any kind of inband noise signals or competing transmitters. If the S/N (ratio to suppress inband noise signals) exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz Df 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds 2 dB. This value is guaranteed for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 2nd-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: 1 fcu_DF = ---------------------------------------------------------2 p 30 kW CDEM In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to section `Configuration of the Receiver'). The BR_Range must be set in accordance to the used baud rate. The T5743 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V DC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
Receiving Characteristics
The RF receiver T5743 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 8. This example relates to ASK mode and the 300-kHz bandwidth version of the T5743. FSK mode and the 600-kHz bandwidth version of the receiver exhibits similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.
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Figure 8. Receiving Frequency Response
0.0 -10.0 -20.0 -30.0 -40.0 without SAW
dP (dB)
-50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -6.0 with SAW
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
df (MHz)
When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the T5743. Low-cost crystals are specified to be within 100 ppm. The XTO deviation of the T5743 is an additional deviation due to the XTO circuit. This deviation is specified to be 30 ppm. If a crystal of 100 ppm is used, the total deviation is 130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.
Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 9, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at Pin MODE. According to section "RF Front-end", the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO).
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Figure 9. Generation of the Basic Clock Cycle
T Clk MODE Divider :14/:10 f 16 DVCC 15 XTO XTO 14 L : USA(:10) H: Europe(:14)
XTO
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following application relevant parameters: * * * * * Timing of the polling circuit including bit check Timing of the analog and digital signal processing Timing of the register programming Frequency of the reset marker IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClkdependent parameters on this electrical characteristics display three conditions for each parameter. * * * Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 s) Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 s) Other applications (TClk is dependent on fXTO and on the logical state of Pin MODE. The electrical characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 TClk TXClk = 4 TClk TXClk = 2 TClk TXClk = 1 TClk
Polling Mode
According to Figure 10, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During TStartup and TBit-check the current consumption is IS = ISon. The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as:
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I Soff T Sleep + I Son ( T Startup + T Bit-check ) I Spoll = ------------------------------------------------------------------------------------------------------------T Sleep + T Startup + T Bit-check During TSleep and TStartup the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup, TBit-check and the start-up time of a connected microcontroller (TStart,C). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. TPreburst TSleep + TStartup + TBit-check + TStart_C
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to Table 9), and the basic clock cycle TClk. It is calculated to be: TSleep = Sleep XSleep 1024 TClk In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to 1. According to Table 8, the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling -- via Pin POLLING/_ON, the receiver can be switched on and off.
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Figure 10. Polling Mode Flow Chart
Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low IS = ISoff TSleep = Sleep XSleep 1024 TClk Clk
Sleep: Sleep: XSleep: XSleep: TClk:: TClk
5-bit word defined by Sleep0 to 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Sleep4 in OPMODE register Extension factor defined by Extension factor defined by XSleepStd according to Table 9 XSleepStd according to Table 9 Basic clock cycle defined by ffXTO Basic clock cycle defined by XTO and Pin MODE and Pin MODE Is defined by the selected baud rate Is defined by the selected baud rate TClk. The baud-rate range is range and TClk.The baud-rate range is defined by Baud0 and Baud1 in the defined by Baud0 and Baud1 in the OPMODE register. OPMODE register.
Start-up mode: The signal processing circuits are enabled. After the start-up time (TStartup) ) Startup all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => high IS = ISon TStartup
TStartup:: TStartup
Bit-check mode: The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE => high IS = ISon TBit-check NO Bit-check OK ?
TBit-check:: TBit-check
Depends on the result of the bit check. Depends on the result of the bit check. If the bit check is ok, TBit-check depends on the If the bit check is ok, TBit-check depends on the number of bits to be checked (NBit-check)) and on number of bits to be checked (NBit-check and on the utilized data rate. the utilized data rate. If the bit check fails, the average time period If the bit check fails, the average time period for that check depends on the selected baudfor that check depends on the selected baudrate range and on TClk.. The baud-rate range is rate range and on TClk The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register defined by Baud0 and Baud1 in the OPMODE register
YES Receiving mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. mC. It can be set to Sleep mode through an OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high IS = ISon OFF command
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Figure 11. Timing Diagram for Complete Successful Bit Check
( Number of checked Bits: 3 ) Bit check ok
IC_ACTIVE Bit check Dem_out Data_out (DATA) 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
TStart-up Start-up mode
T Bit-check Bit-check mode Receiving mode
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between two signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. Assuming a modulation scheme that contains two edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge checks respectively. If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 11 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA. According to Figure 12, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check will be continued. If tee is smaller than T Lim_min or t ee exceeds T Lim_max , the bit check will be terminated and the receiver switches to sleep mode. Figure 12. Valid Time Window for Bit Check
1/fSig tee TLim_min TLim_max
Configuring the Bit Check
Dem_out
For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A "11111..." or a "10101..." sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of 25% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. 13
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TLim_min = Lim_min TXClk TLim_max = (Lim_max -1) TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the section `Receiving Mode'. The lower limit should be set to Lim_min 10. The maximum value of the upper limit is Lim_max = 63. If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving mode due to noise. Figure 13, Figure 14 and Figure 15 illustrate the bit check for the bit-check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the cycle TXClk. Figure 13 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 14 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 15. Figure 13. Timing Diagram During Bit Check
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-checkcounter
0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4
Bit check ok
Bit check ok
1/2 Bit
1/2 Bit
TStart-up Start-up mode
TXClk
TBit-check Bit-check mode
Figure 14. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out
Bit-checkcounter
0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 0
Bit check failed ( CV_Lim < Lim_min )
TStart-up Start-up mode
TBit-check Bit-check mode
TSleep Sleep mode
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Figure 15. Timing Diagram for Failed Bit Check (Condition: CV_Lim Lim_max)
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-checkcounter
0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0
Bit check failed ( CV_Lim >= Lim_max )
TStart-up Start-up mode
TBit-check Bit-check mode
TSleep Sleep mode
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower value for TBit-check resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to Figure 11, the internal data signal is switched to Pin DATA in that case and the data clock is available after the start bit has been detected (Figure 22). A connected microcontroller can be woken up by the negative edge at Pin DATA or by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly. The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 16 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to t ee TDATA_min . This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay Low is limited to TDATA_L_max. This function is employed to ensure a finite response time in programming or switching off the receiver via Pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 18 gives an example where Dem_out remains Low after the receiver has switched to receiving mode.
Digital Signal Processing
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Figure 16. Synchronization of the Demodulator Output
T XClk Clock bit-check counter Dem_out Data_out (DATA)
t ee
Figure 17. Debouncing of the Demodulator Output
Dem_out Data_out (DATA) t DATA_min tDATA_min t DATA_min
tee
t ee
t ee
Figure 18. Steady L State Limited DATA Output Pattern After Transmission
IC_ACTIVE
Bit check Dem_out Data_out (DATA) tDATA_min Start-up mode Bit-check mode Receiving mode
tDATA_L_max
After the end of a data transmission, the receiver remains active. Depending on the bit Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or random noise pulses appear at Pin DATA (see section "Digital Noise Supression"). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than TDATA_min.
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Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via Pin DATA or via Pin POLLING/_ON. When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected microcontroller. Figure 19 illustrates the timing of the OFF command (see also Figure 34). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. Note also that an internal reset for the OPMODE and the LIMIT register will be generated if t1 exceeds the specified values. This item is explained in more detail in the section "Configuration of the Receiver". Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to be "1" during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command the sleep time TSleep elapses. Note that the capacitive load at Pin DATA is limited (see section "Data Interface"). Figure 19. Timing Diagram of the OFF-command via Pin DATA
IC_ACTIVE IC_ACTIVE
t1 t1 t1 t2 t2 t2 t2 t3 t3 t3 t3 t4 t4 t4 t4 t5 t5 t5 t5 t10 t10 t10 t10 t7 t7 t7 t7
Out1 Out1 Out1 (mC) (microcontroller) (microcontroller) (microcontroller
Data_out (DATA) Data_out (DATA)
X X X
Serial bi-directional Serial bi-directional data line data line
X X X
Bit 11 Bit 1 Bit ("1") ("1") ("1") (Start bit) (Start bit) (Start bit) OFF-command OFF-command OFF-command Receiving Receiving mode mode TTSleep TSleep TSleep Sleep Sleep mode Sleep mode Sleep mode Sleep mode TTStart-up TT Start-up Start-up Start-up Start-up mode Start-up mode Start-up mode Start-up mode
Figure 20. Timing Diagram of the OFF-command via Pin POLLING/_ON
IC_ACTIVE ton2 ton3 Bit check ok
POLLING/_ON X
Data_out (DATA)
X
Serial bi-directional data line
X Receiving mode Sleep mode Start-up mode Bit-check mode
X
Receiving mode
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Figure 21. Activating the Receiving Mode via Pin POLLING/_ON
IC_ACTIVE t on1
POLLING/_ON X
Data_out (DATA)
Serial bi-directional data line Sleep mode Start-up mode
X
Receiving mode
Figure 20 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON. The Pin POLLING/_ON must be held to low for the time period ton2. After the positive edge on Pin POLLING/_ON and the delay ton3, the polling mode is active and the sleep time TSleep elapses. This command is faster than using Pin DATA at the cost of an additional connection to the microcontroller. Figure 21 illustrates how to set the receiver to receiving mode via the Pin POLLING/_ON. The Pin POLLING/_ON must be held to Low. After the delay ton1 , the receiver changes from sleep mode to start-up mode regardless the programmed values for TSleep and NBit-check. As long as POLLING/_ON is held to Low, the values for TSleep and NBitcheck will be ignored, but not deleted (see also section "Digital Noise Suppression"). If the receiver is polled exclusively by a microcontroller, TSleep must be programmed to 31 (permanent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON is held to High.
Data Clock
The Pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and Bi-phase coded signals. Generation of the data clock: After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at Pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done, like in the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 22, only two distances between two edges in Manchester and Biphase coded signals are valid (T and 2T). The limits for T are the same as used for the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 11 and Table 12). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) - (Lim_max - Lim_min)/2 (Lim_min + Lim_max) + (Lim_max - Lim_min)/2
(If the result for "Lim_min_2T" or "Lim_max_2T" is not an integer value, it will be round up.) 18
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The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the delay tDelay after the edge on Pin DATA (see figure 22). If the data clock control logic detects a timing or logical error (Manchester code violation), like illustrated in Figure 23 and Figure 24, it stops the output of the data clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see Figure 25). It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the Pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. Figure 22. Timing Diagram of the Data Clock
Preburst Bit check ok T '1' Dem_out '1' '1' '1' '1' 2T '0' '1' '1' '0' '1' '0' Data
Data_out (DATA)
DATA_CLK Start bit Bit-check mode tDelay Receiving mode, data clock control logic active tP_Data_Clk
Figure 23. Data Clock Disappears Because of a Timing Error
Data
Timing error (T ee < T Lim_min OR T Lim_max T Lim_max_2T) T ee
'1' Dem_out
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check active
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Figure 24. Data Clock Disappears Because of a Logical Error
Data Logical error (Manchester code violation)
'1' Dem_out
'1'
'1'
'0'
'1'
'1'
'?'
'0'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check aktive
Figure 25. Output of the Data Clock After a Successful Bit Check
Data Bit check ok
'1' Dem_out
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, bit check active
Start bit
Receiving mode, data clock control logic active
The delay of the data clock is calculated as follows: tDelay = tDelay1 + tDelay2 tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1 depends on the capacitive load CL at Pin DATA and the external pull-up resistor Rpup. For the falling edge, tDelay1 depends additionally on the external voltage VX (see Figure 26, Figure 27 and Figure 34). When the level of Data_In is equal to the level of Data_Out, the data clock is issued after an additional delay tDelay2. Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive load at Pin DATA is exceeded, the data clock disappears (see section "Data Interface").
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Figure 26. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
V X V Ih = 0,65 * V S V Il = 0,35 * V S
Serial bi-directional data line Data_In DATA_CLK
tDelay1 tDelay
tDelay2 tP_Data_Clk
Figure 27. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data_Out
VX V Ih = 0,65 * V S V Il = 0,35 * V S
Serial bi-directional data line Data_In DATA_CLK t Delay1 t Delay t Delay2 tP_Data_Clk
Digital Noise Suppression
Automatic Noise Suppression (see Figure 29)
After a data transmission, digital noise appears on the data output (see Figure 28). To prevent that digital noise keeps the connected microcontroller busy, it can be suppressed in two different ways. If the bit Noise_Disable (Table 10) in the OPMODE register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. The digital noise is suppressed and the level at Pin DATA is High in that case. The receiver changes back to receiving mode, if the bit check was successful. This way to suppress the noise is recommended if the data stream is Manchester or Biphase coded and is active after power on. Figure 30 illustrates the behavior of the data output at the end of a data stream. Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on Pin DATA. The length of the pulse depends on the selected baud-rate range.
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Figure 28. Output of Digital Noise at the End of the Data Stream
Bit check ok Data_out (DATA) DATA_CLK Bit-check mode Receiving mode, data clock control logic active Receiving mode, Receiving mode, bit check aktive bit check aktive Receiving mode, Receiving mode, data clock control data clock control logic active logic active Receiving mode, Receiving mode, bit check aktive bit check aktive Preburst Data Data Digital Noise Digital Noise Bit check ok Bit check ok Digital Noise Digital Noise Preburst Preburst Data Data Digital Noise Digital Noise
Figure 29. Automatic Noise Suppression
Bit check ok Data_out (DATA) DATA_CLK Bit-check mode Receiving mode, data clock control logic active Bit-check mode Receiving mode, data clock control logic active Bit-check mode Preburst Data Bit check ok Preburst Data
Figure 30. Occurence of a Pulse at the End of the Data Stream
Timing error
(tee < TLim_min OR TLim_max < tee
T ee
) < TLim_min_2T OR tee > TLim_max_2T
Data stream
Digital noise
'1' Dem_out
'1'
'1'
Data_out (DATA)
T Pulse
DATA_CLK Receiving mode, data clock control logic active Bit-check mode
Controlled Noise Suppression by the Microcontroller (see Figure 31)
If the bit Noise_Disable (see Table 10) in the OPMODE register is set to 0, digital noise appears at the end of a valid data stream. To suppress the noise, the Pin POLLING/_ON must be set to Low. The receiver remains in receiving mode. Then, the OFFcommand causes the change to the start-up mode. The programmed sleep time (see Table 8) will not be executed because the level at Pin POLLING/_ON is low, but the bit check is active in that case. The OFF-command activates the bit check also if the Pin POLLING/_ON is held to Low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the Pin POLLING/_ON must be set to High. This way to suppress the noise is recommended if the data stream is not Manchester or Bi-phase coded.
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Figure 31. Controlled Noise Suppression
Bit check ok Serial bi-directional data line (DATA_CLK) POLLING/_ON Bit-check mode Receiving mode Start-up Bit-check mode mode Receiving mode Sleep mode Preburst Data OFF-command Digital Noise Bit check ok Preburst Data Digital Noise
Configuration of the Receiver
The T5743 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 4 shows the structure of the registers. According to Table 2 bit 1 defines if the receiver is set back to polling mode via the OFF-command (see section "Receiving Mode") or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. To get a high programming reliability, Bit15 (Stop bit), at the end of the programming operation, must be set to 0. Table 2. Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1 Bit 2 Action
1 0 0
x 1 0
The receiver is set back to polling mode (OFF command) The OPMODE register is programmed The LIMIT register is programmed
Table 3. Effect of Bit 15 on Programming the Register
Bit 15 Action
0 1
The values will be written into the register (OPMODE or LIMIT) The values will not be written into the register
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Table 4. Effect of the Configuration Words Within the Registers
Bit 1 1 OPMODE register BR_Range 0 1 Baud1 Default values of Bit 3...14 0 Baud0 0 BitChk1 0 BitChk0 1 NBit-check Modulation ASK/_ FSK 0 Sleep4 0 LIMIT register Lim_min 0 0 Lim_ min5 0 Lim_ min4 1 Lim_ min3 0 Lim_ min2 1 Lim_ min1 0 Lim_ min0 1 Lim_ max5 1 Lim_ max4 0 Lim_max Lim_ max3 1 Lim_ max2 0 Lim_ max1 0 Lim_max0 1 0 Sleep3 0 Sleep Sleep2 1 Sleep1 1 Sleep0 0 X Sleep XSleepStd 0 Noise Suppression Noise_ Disable 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF-command
0
Default values of Bit 3...14
Table 5 to Table 12 illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits TLim_min and TLim_max as shown in table 11 and table 12. Table 5. Effect of the Configuration Word BR_Range
BR_Range Baud1 Baud0 Baud-Rate Range/Extension Factor for Bit-Check Limits (XLim)
0 0 1 1
0 1 0 1
BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) XLim = 8 (default) BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1
Table 6. Effect of the Configuration Word NBit-check
NBit-check BitChk1 BitChk0 Number of Bits to be Checked
0 0 1 1
0 1 0 1
0 3 (default) 6 9
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Table 7. Effect of the Configuration Bit Modulation
Modulation Selected Modulation
ASK/_FSK 0 1 FSK (default) ASK
Table 8. Effect of the Configuration Word Sleep
Sleep Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 Start Value for Sleep Counter (TSleep = Sleep x Xsleep x 1024 x TClk)
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 0 ... 1 1 1
0 0 0 0 ... 1 ... 1 1 1
0 0 1 1 ... 1 ... 0 1 1
0 1 0 1 ... 0 ... 1 0 1
0 (Receiver is continuously polling until a valid signal occurs) 1 (TSleep 2 ms for XSleep = 1 in US-/ European applications) 2 3 ... 6 (USA: TSleep = 12.52 ms, Europe: TSleep = 12.72 ms) (default) ... 29 30 31 (Permanent sleep mode)
Table 9. Effect of the Configuration Bit XSleep
XSleep XSleepStd Extension Factor for Sleep Time (TSleep = Sleep x Xsleep x 1024 x TClk)
0 1
1 (default) 8
Table 10. Effect of the Configuration Bit Noise Suppression
Noise Suppression Noise_Disable Suppression of the Digital Noise at Pin DATA
0 1
Noise suppression is inactive Noise suppression is active (default)
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Table 11. Effect of the Configuration Word Lim_min
Lim_min (1) (Lim_min < 10 Is Not Applicable) Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lower Limit Value for Bit Check (TLim_min = Lim_min x Lim x TClk)
0 0 0 ... 0 ... 1 1 1 Note:
0 0 0 ... 1 ... 1 1 1
1 1 1 ... 0 ... 1 1 1
0 0 1 ... 1 ... 1 1 1
1 1 0 ... 0 ... 0 1 1
0 1 0 ... 1 ... 1 0 1
10 11 12
21 (default) USA: TLim_min = 342 s, Europe: TLim_min = 348 s)
61 62 63
1. Lim_min is also be used to determine the margins of the data clock control logic (see section "Data Clock").
Table 12. Effect of the Configuration Word Lim_max
Lim_max (1) (Lim_max < 12 Is Not Applicable) Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 Upper Limit Value for Bit Check (TLim_max = (Lim_max - 1) x XLim x TClk)
0 0 0 ... 1 ... 1 1 1 Note:
0 0 0 ... 0 ... 1 1 1
1 1 1 ... 1 ... 1 1 1
1 1 1 ... 0 ... 1 1 1
0 0 1 ... 0 ... 0 1 1
0 1 0 ... 1 ... 1 0 1
12 13 14
41 (default) USA: TLim_max = 652 ms, Europe: TLim_max = 662 s)
61 62 63
1. Lim_max is also be used to determine the margins of the data clock control logic (see section "Data Clock").
Conservation of the Register Information
The T5743 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 32, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset the POR is cancelled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be cancelled via a Low pulse t1 at Pin DATA.
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The RM implies the following characteristics: * * fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller. If the receiver is set back to polling mode via Pin DATA, RM cannot be cancelled by accident if t1 is applied according to the proposal in the section "Programming the Configuration Registers".
By means of that mechanism the receiver cannot lose its register information without communicating that condition via the reset marker RM. Figure 32. Generation of the Power-on Reset
VS POR tRst Data_out (DATA) X
V ThReset
1 / f RM
Programming the Configuration Register Figure 33. Timing of the Register Programming
IC_ACTIVE t1 t2 t3 t4 t5 t6 t7 t9 t8
Out1 (C)
Data_out (DATA) Serial bi-directional data line
X
X Bit 1 ("0") (Start bit) Bit 2 ("1") (Registerselect) Programming frame Receiving mode Bit 14 ("0") (Poll8) Bit 15 ("0") (Stop bit) TSleep TStart-up SleepStart-up mode mode
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Figure 34. Data Interface
V X = 5 V to 20=V V to 20 V V 5 V S = 4.5 V to 5.5 V V to 5.5 V V S = 4.5
T5743 T5743
Rpup DATA
0 ... 20 V
X
Microcontroller Microcontroller
Rpup
0V/5V
0 V / Input 5V
Data_In
Data_In
0 ... 20 V Input Interface Interface
DATA
I/O
I/O
Serial bi-directional data line Serial bi-directional data line
ID
I D
CL
CL
Data_out Data_out
Out1 microcontroller Out1 microcontroller
The configuration registers are programmed serially via the bi-directional data line according to Figure 33 and Figure 34. To start programming, the serial data line DATA is pulled to Low for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down Pin DATA for the time period t7 during t5, the according bit is set to "0". If no programming pulse t7 is issued, this bit is set to "1". All 15 bits are subsequently programmed this way. The time frame to program a bit is defined by t6. Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both in sleep- and in active-mode of the receiver. During programming, the LNA, LO, lowpass filter IF-amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to "1", it represents the OFF-command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered: * t1(min) < t1 < 5632 TClk: t1(min) is the minimum specified value for the relevant BR_Range
Programming respectively OFF-command is initiated if the receiver is not in reset mode.If the receiver is in reset mode, programming respectively Off-command is not initiated and the reset marker RM is still present at Pin DATA. This period is generally used to switch the receiver to polling mode or to start the programming of a register. In reset condition, RM is not cancelled by accident. * t1 > 7936 TClk
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Programming respectively OFF-command is initiated in any case. The registers OPMODE and LIMIT are set to the default values. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If the receiver operates in default mode, this time period for t1 can generally be used. Note that the capacitive load at Pin DATA is limited. Data Interface The data interface (see Figure 34) is designed for automotive requirements. It can be connected via the pull-up resistor Rpup up to 20 V and is short-circuit-protected. The applicable pull-up resistor Rpup depends on the load capacity CL at Pin DATA and the selected BR_range (see Table 13). More detailed information about the calculation of the maximum load capacity at Pin DATA is given in the "Application Hints U3743BM". Table 13. Applicable Rpup
BR_range Applicable Rpup
B0 CL 1 nF B1 B2 B3 B0 CL 100 pF B1 B2 B3
1.6 kW to 47 kW 1.6 kW to 22 kW 1.6 kW to 12 kW 1.6 kW to 5.6 kW 1.6 kW to 470 kW 1.6 kW to 220 kW 1.6 kW to 120 kW 1.6 kW to 56 kW
Figure 35. Application Circuit: fRF = 433.92 MHz without SAW Filter
VS C7 2.2u 10% GND C6 10n 10% IC_ACTIVE R2 Sensitivity reduction 56k to 150k V X = 5 V to 20 V R3 >= 1.6k 20 19 18 17 16 Q1 6.7643MHz C11 12p 2% np0 DATA POLLING/_ON DATA_CLK
T5743
C14 33n 5% C13 10n 10% C3 15p 5% np0 C15 150p 10% 1 2 3 4 5 6 7 8 9 10 SENS DATA IC_ACTIVE POLLING/_ON CDEM DGND DATA_CLK AVCC MODE TEST AGND DVCC 15 MIXVCC XTO 14 LNAGND LNA_IN NC C12 10n 10% C8 150p 10% LFGND 13 LF 12 LFVCC 11
COAX
C17 3.3p 5% np0
C16 100p 5% np0 L2 TOKO LL2012 F22NJ 22n 5%
R1 820 5% C9 4.7n 5%
C10 1n 5%
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Figure 36. Application Circuit: fRF = 315 MHz without SAW Filter
VS C7 2.2u 10% GND C6 10n 10% IC_ACTIVE R2 Sensitivity reduction 56k to 150K V X = 5 V to 20 V R3 >= 1.6k 20 19 18 17 16 15 Q1 4.906MHz C11 15p 2% np0 DATA POLLING/_ON DATA_CLK
T5743
C14 33n 5% C13 10n 10% C3 33p 5% np0 C15 150p 10% 1 2 3 4 5 6 7 8 9 10 SENS DATA IC_ACTIVE POLLING/_ON CDEM DGND DATA_CLK AVCC MODE TEST AGND DVCC MIXVCC LNAGND LNA_IN NC C12 10n 10% C8 150p 10%
XTO 14 LFGND 13 LF 12 LFVCC 11
COAX
C17 3.3p 5% np0
C16 100p 5% np0 L2 TOKO LL2012 F39NJ 39n 5%
R1 820 5% C9 4.7n 5%
C10 1n 5%
Figure 37. Application Circuit: fRF = 433.92 MHz with SAW Filter
VS C7 2.2u 10% GND C6 10n 10% IC_ACTIVE R2 Sensitivity reduction 56k to 150k V X = 5 V to 20 V R3 >= 1.6k 20 19 18 17 16 15 Q1 6.7643MHz C11 12p 2% np0 DATA POLLING/_ON DATA_CLK
T5743
C14 33n 5% C13 10n 10% C3 22p 5% np0 C15 150p 10% 1 2 3 4 5 6 7 8 9 10 SENS DATA IC_ACTIVE POLLING/_ON CDEM DGND DATA_CLK AVCC MODE TEST AGND DVCC MIXVCC LNAGND LNA_IN NC C12 10n 10% C8 150p 10%
XTO 14 LFGND 13 LF 12 LFVCC 11
C16 100p 5% np0
C17
8,2p 5% np0 L3 TOKO LL2012 F27 NJ 27n 5%
R1 820 5% C9 4.7n 5%
COAX
L2 TOKO LL2012 F33NJ 1 IN 2 IN_GND 33n 3 C2 5% 4 8.2p CASE_GND 5% np0 B3555
OUT OUT_GND CASE_GND
5 6 7 8
C10 1n 5%
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Figure 38. Application Circuit: fRF = 315 MHz with SAW Filter
VS C7 2.2u 10% GND C6 10n 10% IC_ACTIVE R2 Sensitivity reduction 56k to 150k V X = 5 V to 20 V R3 >= 1.6k 20 19 18 17 16 15 Q1 4.906MHz C11 15p 2% np0 DATA POLLING/_ON DATA_CLK
T5743
C14 33n 5% C13 10n 10% C3 47p 5% np0 C15 150p 10% 1 2 3 4 5 6 7 8 9 10 SENS DATA IC_ACTIVE POLLING/_ON CDEM DGND DATA_CLK AVCC MODE TEST AGND DVCC MIXVCC LNAGND LNA_IN NC C12 10n 10% C8 150p 10%
XTO 14 LFGND 13 LF 12 LFVCC 11
C16 100p 5% np0
C17
22p 5% np0 L3 TOKO LL2012 F47NJ 47n 5%
R1 820 5% C9 4.7n 5%
COAX
L2 TOKO LL2012 F82NJ 1 2 82n 3 C2 5% 4 10p 5% np0
IN IN_GND CASE_GND B3551
OUT OUT_GND
5 6
7 CASE_GND 8
C10 1n 5%
Absolute Maximum Ratings
Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 W Symbol VS Ptot Tj Tstg Tamb Pin_max -55 -40 Min. Max. 6 1000 150 +125 +105 10 Unit V mW
C C C
dBm
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 100 Unit K/W
31
4569A-RKE-12/02
Electrical Characteristics
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
6.76438 MHz Osc. (MODE: 1) Parameter Basic clock cycle Extended basic clock cycle Test Conditions MODE = 0 (USA) MODE = 1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 Symbol Min. Typ. Max. Basic Clock Cycle of the Digital Circuitry TClk 2.0697 16.6 8.3 4.1 2.1 Sleep XSleep 1024 2.0697 1855 1061 1061 663 2.0697 16.6 8.3 4.1 2.1 Sleep XSleep 1024 2.0697 1855 1061 1061 663 2.0383 16.3 8.2 4.1 2.0 Sleep XSleep 1024 2.0383 1827 1045 1045 653 2.0383 16.3 8.2 4.1 2.0 Sleep XSleep 1024 2.0383 1827 1045 1045 653 1/fXTO/10 1/fXTO/14 8 TClk 4 TClk 2 TClk 1 TClk 1/fXTO/10 1/fXTO/14 8 TClk 4 TClk 2 TClk 1 TClk s s s s s s 4.90625 MHz Osc. (MODE: 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit
TXClk
Polling Mode Sleep time (see Sleep and XSleep Figure 10, are defined in the Figure 19, and OPMODE register Figure 33) Start-up time (see Figure 10, and Figure 11) BR_Range0 BR_Range1 BR_Range2 BR_Range3 Sleep XSleep 1024 TClk 896.5 512.5 512.5 320.5 TClk Sleep XSleep 1024 TClk 896.5 512.5 512.5 320.5 TClk
TSleep
ms
TStartup
s s s s
Time for bit check (see Figure 10)
Average bit-check time while polling, no RF applied (see Figure 14, and Figure 15) BR_Range0 BR_Range1 BR_Range2 BR_Range3 Bit-check time for a valid input signal fSig , (see Figure 11) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9
TBit-check
0.45 0.24 0.14 0.08
0.45 0.24 0.14 0.08
ms ms ms ms
TBit-check
3/fSig 6/fSig 9/fSig
3.5/fSig 6.5/fSig 9.5/fSig
3/fSig 6/fSig 9/fSig
3.5/fSig 6.5/fSig 9.5/fSig
1 X TXClk 3/fSig 6/fSig 9/fSig
1 TClk 3.5/fSig 6.5/fSig 9.5/fSig
ms ms ms ms MHz MHz kBaud kBaud kBaud kBaud
Receiving Mode Intermediate frequency Baud-rate range MODE = 0 (USA) MODE = 1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 165 83 41.4 20.7 165 83 41.4 20.7 163 81 40.7 20.4 163 81 40.7 20.4 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk s s s s fIF 1.0 1.8 3.2 5.6 1.0 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.0 1.8 3.2 5.6 10.0 fXTO 64/314 fXTO 64/432.92 BR_Range0 2 ms/TClk BR_Range1 2 ms/TClk BR_Range2 2 ms/TClk BR_Range3 2 ms/TClk
BR_Range
Minimum time period between edges at Pin DATA (see Figure 7, Figure 17 and Figure 18, with the exception of parameter TPulse)
tDATA-min
32
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4569A-RKE-12/02
T5743
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
6.76438 MHz Osc. (MODE: 1) Parameter Maximum Low period at Pin DATA (see Figure 7 and Figure 18) Delay to activate the start-up mode (see Figure 21) OFF- command at Pin POLLING/_ON (see Figure 20) Delay to activate the sleep mode (see Figure 20) Pulse on Pin DATA at the end of a data stream (see Figure 30) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 (see Figure 31) fRM BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR (see Figure 19 and Figure 33) 3367 2277 1735 1464 16.43 795 265 11650 11650 11650 11650 3311 2243 1709 1442 16.18 783 261 11470 11470 11470 11470 1624 TClk 1100 TClk 838 TClk 707 TClk 7936 TClk 384.5 TClk 128 TClk 63.5 TClk 256 TClk 512 TClk 5632 TClk 5632 TClk 5632 TClk 5632 TClk 385.5 TClk 128 TClk 63.5 TClk 256 TClk 512 TClk s s s s s s s 117.9 117.9 119.8 119.8 TPulse 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 TClk 4 TClk 2 TClk 1 TClk 8 TClk 4 TClk 2 TClk 1 TClk s s s s Test Conditions BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDATA_L_max 2152 1076 538 270 2152 1076 538 270 2120 1060 530 265 2120 1060 530 265 130 TXClk 130 TXClk 130 TXClk 130 TXClk 9.5 TClk 130 TXClk 130 TXClk 130 TXClk 130 TXClk 10.5 TClk s s s s Symbol Min. Typ. Max. 4.90625 MHz Osc. (MODE: 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit
Ton1
19.7
21.8
19.4
21.5
s
Ton2
16.6
16.4
8 TClk
s
Ton3
17.6
19.7
17.4
19.4
8.5 TClk
9.5 TClk
s
Configuration of the Receiver Frequency of the reset marker Programming start pulse (see Figure 19 and Figure 33) 1 -----------------------------4096 T Clk 1 -----------------------------4096 T Clk Hz
t1
Programming delay period Synchronization pulse Delay until of the program window starts Programming window Time frame of a bit (see Figure 33) Programming pulse (see Figure 19 and Figure 33)
t2 t3
798 265
786 261
t4
131
131
129
129
s
t5
530
530
522
522
s
t6
1060
1060
1044
1044
s
t7
132
529
130
521
64 TClk
256 TClk
s
33
4569A-RKE-12/02
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
6.76438 MHz Osc. (MODE: 1) Parameter Equivalent acknowledge pulse: E_Ack (see Figure 33) Equivalent time window (see Figure 33) OFF-bit programming window (see Figure 19) Data Clock Minimum delay time between edge at DATA and DATA_CLK (see Figure 26 and Figure 27) Pulswidth of negative pulse at Pin DATA_CLK (see Figure 26 and Figure 27) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tP_DATA_CLK 66.2 33.1 16.56 8.3 66.2 33.1 16.56 8.3 65.2 32.6 16.3 8.2 65.2 32.6 16.3 8.2 4 TXClk 4 TXClk 4 TXClk 4 TXClk 4 TXClk 4 TXClk 4 TXClk 4 TXClk s s s s 0 0 0 0 16.6 8.3 4.15 2.07 0 0 0 0 16.3 8.2 4.08 2.04 0 0 0 0 1 TXClk 1 TXClk 1 TXClk 1 TXClk s s s s Test Conditions Symbol Min. Typ. Max. 4.90625 MHz Osc. (MODE: 0) Min. Typ. Max. Variable Oscillator Min. 128 TClk Typ. Max. 128 TClk Unit
t8
265
265
261
261
s
t9
534
534
526
526
258 TClk
258 TClk
s
t10
930
930
916
916
449.5 TClk
449.5 TClk
s
tDelay2
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Current consumption Test Conditions Sleep mode (XTO and polling logic active) IC active (start-up-, bit check-, receiving mode) Pin DATA = H FSK ASK LNA Mixer (Input Matched According to Figure 6) Third-order intercept point LO spurious emission at RFIn Noise figure LNA and mixer (DSB) LNA_IN input impedance at 433.92 MHz at 315 MHz LNA/mixer/IF amplifier Required according to I-ETS 300220 IIP3 ISLORF NF ZiLNA_IN IP1db -28 -73 7
1.0 || 1.56 1.3 || 1.0
Symbol ISoff
Min.
Typ. 170
Max. 276
Unit A
ISon
7.5 7.1
9.1 8.7
mA mA dBm
-57
dBm dB
kW || pF kW || pF
1 dB compression point (LNA, mixer, Referred to RFin IF amplifier)
-40
dBm
34
T5743
4569A-RKE-12/02
T5743
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Maximum input level Test Conditions BER 10 , FSK mode ASK mode
-3
Symbol Pin_max
Min.
Typ.
Max. -22 -20
Unit dBm dBm MHz dBC/Hz dBC/Hz dBC MHz/V
Local Oscillator Operating frequency range VCO Phase noise VCO/LO fosc = 432.92 MHz at 1 MHz at 10 MHz at fXTO KVCO For best LO noise (design parameter) R1 = 820 W C9 = 4.7 nF C10 = 1 nF The capacitive load at Pin LF is limited if bit check is used. The limitation therefore also applies to self polling. XTO crystal frequency, appropriate load capacitance must be connected to XTAL fXTAL = 6.764375 MHz (EU) fXTAL = 4.90625 MHz (US) fXTO = 6.764 MHz, fXTO = 4.906 MHz fVCO L (fm) 299 -93 -113 -55 190 449 -90 -110 -47
Spurious of the VCO VCO gain Loop bandwidth of the PLL
BLoop
100
kHz
Capacitive load at Pin LF
CLF_tot
10
nF
XTO operating frequency
fXTO RS C0
-30 ppm
fXTAL
+30 ppm 150 220 6.5
MHz
W W
Series resonance resistor of the crystal Static capacitance at Pin XTO to GND Analog Signal Processing Input sensitivity ASK 300 kHz IF-filter
pF
Input matched according to Figure 6 ASK (level of carrier) BER 10-3, BW = 300 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25C, fIF = 1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3
PRef_ASK -109 -107 -106 -104 -111 -109 -108 -106 -113 -111 -110 -108 dBm dBm dBm dBm
35
4569A-RKE-12/02
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Input sensitivity ASK 600 kHz IF-filter Test Conditions Input matched according to Figure 6 ASK (level of carrier) BER 10-3, BW = 600kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25C, fIF = 1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3 300 kHz and 600 kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz, PASK = PRef_ASK + DPRef 300 kHz version fin = 433.92 MHz/315 MHz fIF = 0.89 MHz to 1.11 MHz fIF = 0.86 MHz to 1.14 MHz PASK = PRef_ASK + DPRef 600 kHz version fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + DPRef Input sensitivity FSK 300 kHz IF-filter Input matched according to Figure 6 BER 10-3, BW = 300 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25C fIF = 1 MHz BR_Range0 df = 16 kHz df = 10 kHz to 30 kHz BR_Range1 df = 16 kHz df = 10 kHz to 30 kHz BR_Range2 df = 16 kHz df = 10 kHz to 30 kHz BR_Range3 df = 16 kHz df = 10 kHz to 30 kHz PRef_FSK -101 -99 -99 -97 -97.5 -95.5 -95.5 -93.5 -104 -105.5 -105.5 -103.5 -103.5 -102 -102 -100 -100 dBm dBm dBm dBm dBm dBm dBm dBm Symbol Min. Typ. Max. Unit
PRef_ASK -108 -106.5 -106 -104
DPRef
-110 -108.5 -108 -106
-112 -110.5 -110 -108 -1.5
dBm dBm dBm dBm dB
Sensitivity variation ASK for the full operating range compared to Tamb = 25C, VS = 5 V Sensitivity variation ASK for full operating range including IF-filter compared to Tamb = 25C, VS = 5 V,
+2.5
DPRef
+5.5 +7.5
-1.5 -1.5
dB dB
DPRef
+5.5 +7.5
-1.5 -1.5
dB dB
PRef_FSK
-102
PRef_FSK
-100.5
PRef_FSK
-98.5
36
T5743
4569A-RKE-12/02
T5743
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Input sensitivity FSK 600 kHz IF-filter Test Conditions Input matched according to Figure 6 BER 10-3, BW = 600 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25C fIF = 1 MHz BR_Range0 df = 16 kHz df = 10 kHz to 100 kHz BR_Range1 df = 16 kHz df = 10 kHz to 100 kHz BR_Range2 df = 16 kHz df = 10 kHz to 100 kHz BR_Range3 df = 16 kHz df = 10 kHz to 100 kHz Sensitivity variation FSK for the full operating range compared to Tamb = 25C, VS = 5 V Sensitivity variation FSK for the full operating range including IF-filter compared to Tamb = 25C, VS = 5 V 300 kHz and 600 kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + DPRef 300 kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.89 MHz to 1.11 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + DPRef 600 kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.85 MHz to 1.15 MHz fIF = 0.80 MHz to 1.20 MHz fIF = 0.74 MHz to 1.26 MHz PFSK = PRef_FSK + DPRef S/N ratio to suppress inband noise ASK mode signals. Noise signals may have any FSK mode modulation scheme Dynamic range RSSI ampl. Lower cut-off frequency of the data filter Recommended CDEM for best performance CDEM = 33 nF
1 f cu_DF = ---------------------------------------------------------2 p 30 kW CDEM
Symbol
Min.
Typ.
Max.
Unit
PRef_FSK
-101 -99 -99 -97 -97.5 -95.5 -95.5 -93.5 +3
-104
-105.5 -105.5 -103.5 -103.5 -102 -102 -100 -100 -1.5
dBm dBm dBm dBm dBm dBm dBm dBm dB
PRef_FSK
-102
PRef_FSK
-100.5
PRef_FSK
-98.5
DPRef
DPRef
+6 +8 +11
-2 -2 -2
dB dB dB
DPRef
+6 +8 +11
-2 -2 -2
dB dB dB
SNRASK SNRFSK DRRSSI fcu_DF 0.11 60 0.16 39 22 12 8.2
12 3
dB dB dB
0.20
kHz nF nF nF nF
BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3
CDEM
37
4569A-RKE-12/02
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Edge-to-edge time period of the input data signal for full sensitivity Test Conditions BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 RSense connected from Pin Sens to VS, input matched according to Figure 6 RSense = 56 kW, fin = 433.92 MHz, at BW = 300 kHz at BW = 600 kHz RSense = 100 kW, fin = 433.92 MHz, at BW = 300 kHz at BW = 600 kHz RSense = 56 kW, fin = 315 MHz, at BW = 300 kHz at BW = 600 kHz RSense = 100 kW, fin = 315 MHz, at BW = 300 kHz at BW = 600 kHz Reduced sensitivity variation over full operating range Reduced sensitivity variation for different values of RSense RSense = 56 kW RSense = 100 kW PRed = PRef_Red + DPRed Values relative to RSense = 56 kW RSense = 56 kW RSense = 68 kW RSense = 82 kW RSense = 100 kW RSense = 120 kW RSense = 150 kW PRed = PRef_Red + DPRed Threshold voltage for reset
DPRed DPRed DPRed DPRed DPRed DPRed DPRed
Symbol
Min. 270 156 89 50
Typ.
Max. 1000 560 320 180
Unit s s s s
tee_sig
Upper cut-off frequency data filter
fu
2.8 4.8 8.0 15.0
3.4 6.0 10.0 19.0
4.0 7.2 12.0 23.0
kHz kHz kHz kHz dBm (peak level)
Reduced sensitivity
PRef_Red
-71 -67 -80 -76 -72 -68 -81 -77 5 6
-76 -72 -85 -81 -77 -73 -86 -82 0 0
-81 -77 -90 -86 -82 -78 -91 -87 0 0
dBm dBm dBm dBm dBm dBm dBm dBm dB dB
0 -3.5 -6.0 -9.0 -11.0 -13.5 1.95 2.8 3.75
dB dB dB dB dB dB V
VThRESET
38
T5743
4569A-RKE-12/02
T5743
Electrical Characteristics (Continued)
All parameters refer to GND, Tamb = -40C to +105C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C) Parameters Digital Ports Data output - Saturation voltage Low - max voltage at Pin DATA - quiescent current - short-circuit current - ambient temperature in case of permanent short-circuit Data input - Input voltage Low - Input voltage High DATA_CLK output - Saturation voltage Low - Saturation voltage High IC_ACTIVE output - Saturation voltage Low - Saturation voltage High POLLING/_ON input - Low level input voltage - High level input voltage MODE input - Low level input voltage - High level input voltage TEST input - Low level input voltage Iol 12 mA Iol = 2 mA Voh = 20 V Vol = 0.8 V to 20 V Voh = 0 V to 20 V Vol Vol Voh Iqu Iol_lim tamb_sc 13 0.35 0.08 0.8 0.3 20 20 45 85 0.35 VS V V V A mA C Test Conditions Symbol Min. Typ. Max. Unit
30
VIl Vich IDATA_CLK = 1 mA IDATA_CLK = -1 mA IIC_ACTIVE = 1 mA IIC_ACTIVE = -1 mA Receiving mode Polling mode Division factor = 10 Division factor = 14 Test input must always be set to Low Vol Voh Vol Voh VIl VIh VIl VIh VIl
0.65 VS VS-0.4 V
0.1 VS-0.15 V 0.1 VS-0.15 V
V V V V V V V V V V V
0.4
VS-0.4 V
0.4
0.8 VS
0.2 VS
0.8 VS
0.2 VS 0.2 VS
39
4569A-RKE-12/02
Ordering Information
Extended Type Number T5743P3-TG T5743P3-TGQ T5743P6-TG T5743P6-TGQ Package SO20 SO20 SO20 SO20 Remarks Tube, IF bandwidth of 300 kHz Taped and reeled, IF bandwidth of 300 kHz Tube, IF bandwidth of 600 kHz Taped and reeled, IF bandwidth of 600 kHz
Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35 0.25 10.50 10.20 11
0.4 1.27 11.43 20
0.25 0.10
technical drawings according to DIN specifications
1
10
40
T5743
4569A-RKE-12/02
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